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RTL Modeling with SystemVerilog for Simulation and Synthesis : Using SystemVerilog for ASIC and FPGA Design
Author(s)
Stuart Sutherland
RTL Modeling with SystemVerilog for Simulation and Synthesis : Using SystemVerilog for ASIC and FPGA Design
Author(s)
Stuart Sutherland
Published
2017
Format
Paperback 488 pages
ISBN
978-1-5467-7634-5
Format
Paperback 488 pages
ISBN
978-1-5467-7634-5
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